The fabrication sequence of integrated circuits often includes several patterning processes. The patterning processes may define a layer of conductors, such as a patterned metal or polysilicon layer, or may define isolation structures, such as trenches. In many cases the trenches are filled with an insulating, or dielectric, material. This insulating material can serve several functions. For example, in some applications the material serves to both electrically isolate one region of the IC from another, and electrically passivate the surface of the trench. The material also typically provides a base for the next layer of the semiconductor structure to be built upon.
As semiconductor design has advanced, the feature size of semiconductor devices has dramatically decreased. Many circuits now have features, such as traces or trenches, less than a micron across. While the reduction in feature size has allowed higher device density, more chips per wafer, more complex circuits, lower operating power consumption and lower cost, among other benefits, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries.
An example of the type of manufacturing challenge presented by sub-micron devices is the ability to completely fill a narrow trench in a void-free manner. To fill a trench with silicon oxide, a layer of silicon oxide is first deposited on the patterned substrate. The silicon oxide layer typically covers the field, as well as walls and bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench. As the trench gets narrower and the aspect ratio (the ratio of the trench height to the trench width) increases, it becomes more likely that the opening of the trench will “pinch off”.
Pinching off a trench may trap a void within the trench. Voids resulting from pinching-off are undesirable as they can reduce the yield of good chips per wafer and the reliability of the devices. Under certain conditions, the void will be filled during a reflow process, for example where the deposited silicon oxide is doped and experiences viscous flow at elevated temperatures. However, as the trench becomes narrower, it becomes more likely that the void will not be filled during the reflow process. Moreover, several types of applications call for the deposition of undoped silicon oxide, which is difficult to reflow even at elevated temperature.
One possible solution to this problem is to anneal the oxide layer at high temperatures. Although successful in the past, this solution is no longer applicable in certain situations. New materials, such as nickel silicide, used in advanced semiconductor designs, have lowered thermal budgets, thus rendering some temperature/duration ranges of annealing unfeasible.
Therefore, it is desirable to be able to fill narrow gaps with dielectric material in a void-free manner. It is also desirable to do so without exceeding a thermal budget.